Hereinafter, the term “structures” is defined as all types of elements which are produced by various chemical and/or physical processes directly on a wafer or which are externally produced and are joined to the wafer by any alignment process or placement process.
Examples of structures which are produced directly on the wafer are vapor-deposited conductor paths, ICs produced lithographically on the wafer, for example CMOS or TTL logics, sensors, etching structures, MEMS, etc.
On the other hand, a wafer can also be provided with components by an insertion process. The most common example for an insertion process would be the application of chips in a chip-to-wafer process by a pick-and-place (i.e., transfer) device. These components represent 3D expansions of the basic structure of the wafer. These components are also encompassed by the term “structures,” as used herein.
All the aforementioned structures can have deviations from the ideal. For example, conductor paths can have slight distortions due to faults in the mask. It would furthermore be conceivable that the conductor paths have indeed been correctly produced on the wafer, but in a subsequent bond process such a high pressure is applied to the wafer that the conductor's surface and thus also the conductor paths are distorted. Furthermore distortions of the surface can arise due to other technical-physical and/or chemical influences, for example by thermal stresses, thermal shock, inherent stresses, etc. Similar considerations apply to all structures which have been applied directly to a wafer.
In structures which are applied by an insertion process to the wafer surface, the positioning and/or alignment of the structure can be faulty. In this case distortion is defined as distortion of the applied structure itself, predominantly caused by torsion and shearing.
Alignment in bond processes, especially chip-to-wafer methods, is becoming increasingly more important due to the 3D technology which is becoming more and more important in combination with advancing miniaturization. This acquires importance mainly in applications in which alignment accuracies of less than 2 μm for all sites located on the wafer are desired. The importance and demands on the accuracy of alignment technology are still increasing greatly for desired accuracies less than 1 μm, especially less than 0.5 μm, or less than 0.25 μm.
Due to the fact that the structures are becoming smaller and smaller, but the wafers at the same time are becoming larger and larger, structures which are very well aligned to one another may be present in the vicinity of alignment marks, while at other positions of the wafer the structures have not been correctly or at least not optimally placed.
For this reason, metrology tools are used for checking of alignment accuracies. EP 2299472 shows a method in which it is possible to measure the entire surface of a wafer in order to obtain information about the positions of the structures on the surface of each wafer.
The structures mentioned here can be deformed in exactly the same manner by high pressures, thermal stresses, inherent stress, thermal shocks, etc.
The object of this invention is to develop a generic device and a generic method such that checking of the alignment accuracy and/or of the distortion more efficiently and more accurately is enabled.
This object is achieved with the features of the claims. Advantageous developments of the invention are given in the dependent claims. All combinations of at least two of the features given in the specification, the claims and/or the figures also fall within the scope of the invention. At the given value ranges, values within the indicated limits will also be considered to be disclosed as boundary values and will be claimed in any combination.